Three-dimensional (3D) deconvolution is widely used in many computer vision applications.\nHowever, most previous works have only focused on accelerating two-dimensional (2D)\ndeconvolutional neural networks (DCNNs) on Field-Programmable Gate Arrays (FPGAs), while the\nacceleration of 3D DCNNs has not been well studied in depth as they have higher computational\ncomplexity and sparsity than 2D DCNNs. In this paper, we focus on the acceleration of both 2D and 3D\nsparse DCNNs on FPGAs by proposing efficient schemes for mapping 2D and 3D sparse DCNNs on\na uniform architecture. Firstly, a pruning method is used to prune unimportant network connections\nand increase the sparsity of weights. After being pruned, the number of parameters of DCNNs is\nreduced significantly without accuracy loss. Secondly, the remaining non-zero weights are encoded\nin coordinate (COO) format, reducing the memory demands of parameters. Finally, to demonstrate\nthe effectiveness of our work, we implement our accelerator design on the Xilinx VC709 evaluation\nplatform for four real-life 2D and 3D DCNNs. After the first two steps, the storage required of\nDCNNs is reduced up to 3.9*. Results show that the performance of our method on the accelerator\noutperforms that of the our prior work by 2.5* to 3.6* in latency.
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